The present invention relates to a driving circuit used suitably for driving a capacitive load such as liquid crystal panel.
With respect to liquid crystal panel used in portable telephone or hand-held computer, a tendency of upsizing the same is promoted simultaneously with that of reduction in electric power consumption of the same year by year. In this respect, an equivalent capacity of a liquid crystal panel to be covered by a single driving circuit corresponds to a total capacity of a plurality of liquid crystal cells on a single common line or a single segment line. Such equivalent capacity depends upon an area of its panel, so that a value thereof reaches several thousand pF to several ten thousand pF, besides upsizing of liquid crystal panel advances year after year, and thus the equivalent capacity increases much more.
First of all, a first conventional example will be described hereunder. FIG. 12 is a circuit diagram showing an archaic conventional driving circuit 100 which is arranged in such that the maximum value of a load to be driven is predetermined, whereby an operating current has been set in its design stage wherein reference characters MP101 to MP105 designate PMOS transistors, and MN101 to MN103 NMOS transistors, respectively. It is to be noted that a back gate of a PMOS transistor is connected to a high potential power source VDD, while a back gate of an NMOS transistor is connected to a low potential power source VSS, although such arrangement is not specifically explained hereinafter.
Reference numeral 101 designates a differential amplifying circuit composed of MP101, MP102, MP104, MN101, and MN102, 102 a noninverting input terminal, 103 an inverting input terminal, 104 an output circuit composed of MN103, MP105, and a phase compensating capacitor C102, 105 an output terminal, and C101 a capacitive load, respectively. In this arrangement, MP104,and MP105 are connected to MP103 in a current mirror fashion, so that a bias current corresponding to a current source I101 flows through them.
FIG. 13 is a waveform diagram of voltages and electric currents in respective sections of the driving circuit 100 wherein the inverting input terminal 103 is commonly connected to the output terminal 105 to operate the whole arrangement as a voltage follower. In the case shown in FIG. 13, VDD=0 V, VSS=xe2x88x9210 V, the capacitive load C101 is 10,000 pF, and a driving signal Vin (200 xcexcs cycle, and 50% duty(duty ratio)) is fed to the noninverting input terminal 102. In the figure, time is plotted as abscissa and drain voltage Vd(#) of a transistor #, drain current Id(#) of the transistor #, and current consumption Ivdd flowing through the power source VDD as ordinates, respectively.
A comparatively large current consumption Ivdd is observed for a comparatively long period of time from the time at which the driving signal Vin at the input terminal 102 varies. At least 258.26 xcexcA was required for the current Ivdd heretofore. Furthermore, the driving circuit 100 is arranged in such that the current of I101 and each size ratio of MP104 and MP105 with respect to MP103 have been previously determined in response to the possible maximum capacity of the capacitive load C101, whereby a bias current flowing through MP104 and MP105 is decided. In this respect, however, since such bias current flows in even a steady state wherein the driving signal Vin does not vary, there is such a problem that the bias current (idling current) is useless, so that its driving efficiency decreases in the case where a small load is driven.
A second conventional example will be described. FIG. 14 is a circuit diagram showing a driving circuit 120 which is obtained by improving the driving circuit 100 shown in FIG. 12 in such that an operating current is increased tentatively for only a timing period where a driving signal Vin varies and which has been proposed by Japanese Unexamined Patent Publication No. 221560/1995. In FIG. 14, reference characters MP121 through MP125 designate PMOS transistors, while MN121 through MN124 NMOS transistors, respectively.
Reference character 121 denotes a differential amplifying circuit composed of MP121, MP122, MP124, MN121, and MN122, 122 a noninverting input terminal, 123 an inverting input terminal, 124 an output circuit composed of MN123, MP125, and a phase compensating capacitor C122, 125 an output terminal, and C121 a capacitive load, respectively. MP124 and MP125 are connected to MP123 in a current mirror fashion. MN124, and resistors R121 and R122 constitute a bias switching circuit 126. Reference numeral 127 designates a control terminal.
In the driving circuit 120 shown in FIG. 14, the inverting input terminal 123 is commonly connected with the output terminal 125, so that the whole arrangement operates as a voltage follower. In the arrangement, a voltage with xe2x80x9cHixe2x80x9d level is applied to the control terminal 127 in exact timing with a transition of the driving signal Vin by its corresponding term to bring MN124 into conduction, so that R122 is short-circuited, whereby an operating current flowing through MP124 and MP125 is increased to supply a driving current requested by the capacitive load C121. Accordingly, an operating current in the case where it is not required for driving operation decreases and its driving efficiency is remarkably improved as compared with the driving circuit 100 shown in FIG. 12.
However, although the driving circuit 120 can cope with a load which has been predetermined beforehand, its operating current can be switched only in two stages, so that there is such a problem that a driving force becomes insufficient with respect to a larger load than that forecasted, and on the contrary, a useless current flows with respect to a smaller load than that which has been forecasted. Moreover, when a frequency of a driving pulse becomes high, a rate of time occupied by a term wherein a current is allowed to increase builds up also so that an effect for saving electric current decreases. In addition, since electric current available efficiency itself for a driving period of time is not different from that of the circuit shown in FIG. 12, an electric current increases when its load capacity increases.
A third conventional example will be described. FIG. 15 is a circuit diagram showing a driving circuit 140 wherein a voltage change in a differential circuit is converted into current change to increase its output driving force. The driving circuit 140 is called also by the name of xe2x80x9ctransconductance amplifierxe2x80x9d and which is known from long ago. In FIG. 15, reference characters MP141 to MP146 designate PMOS transistors, and MN141 to MN144 NMOS transistors, respectively.
Reference numeral 141 denotes a differential amplifying circuit composed of MP141, MP142, MP145, MN141, and MN142, 142 a noninverting input terminal, 143 an inverting input terminal, 144 an output circuit composed of MP146 and MN 143, 145 an output terminal, and C141 a capacitive load, respectively. MN144 and MP144 are served for supplying a drain voltage change in MN141 to MP146. To MN143 is supplied a drain voltage in MN142. A bias current corresponding to an electric current of a current source I141 is flowing through MP145 by means of MP143.
FIG. 16 is a waveform diagram of voltages and electric currents in respective sections of the driving circuit 140 wherein the inverting input terminal 143 is commonly connected with the output terminal 145 to operate the whole arrangement as a voltage follower. In the case shown in FIG. 16, VDD=0 V, VSS=xe2x88x9210 V, the capacitive load C141 is 10,000 pF and a driving signal Vin (200 xcexcs cycle, and 50% duty) is fed to the noninverting input terminal 142. In the figure, time is plotted as abscissa and drain voltage Vd(#) of a transistor #, drain current Id(#) of the transistor #, and current consumption Ivdd flowing through the power source VDD as ordinates, respectively. The Ivdd was 228.18 xcexcA in its steady state. It is to be noted that as to a waveform the polarity of which has been inverted in FIG. 16, xe2x80x9cxe2x88x92xe2x80x9d (bar) is applied over a symbol of the corresponding voltage or electric current.
In the driving circuit 140, a drain of MN141 is connected directly with a gate of MN144, while a drain of MN141 is connected electrically to MP146 through MN144 and MP144. Accordingly, an operating current of MN142 determines that of MN 143, and an operating current of MN141 determines that of MP146. Hence, when a size ratio of MN142 to MN143 as well as a size ratio of MN141 to MP146 are made remarkable, a large capacitive load C141 can be driven. However, such arrangement as described above brings about a problem of an increase of idling current in MN143 and MN146. Furthermore, an idling current in the differential amplifying circuit 141 must be flowing all the time and cannot be reduced.
A forth conventional example will be described. FIG. 17 is a circuit diagram showing a driving circuit 160 which is arranged in such that a change in voltage output of a differential amplifying circuit is converted into electric current, and to which is applied positive feedback to increase a drivability. This arrangement is called by the name of adaptive bias system and which has been proposed by Japanese Unexamined Patent Publication Nos. 104663/1994, 22741/1998 and U.S. Pat. No. 5,471,171 etc. In FIG. 17, reference numerals MP161 through MP167 designate PMOS transistors, and MN161 through MN164 NMOS transistors, respectively.
Reference character 161 denotes a differential amplifying circuit composed of MP161, MP162, MP166, MN161, and MN162, 162 a noninverting input terminal, 163 an inverting input terminal, 164 an output circuit composed of MN164, MP167, and a phase compensating capacitor C162, 165 an output terminal, and C161 a capacitive load, respectively. MP165 through MP167 are connected with MP164 in a current mirror fashion, and through which a bias current corresponding to a value of electric current obtained by summing up those flowing through a current source I161 and MP163 is flowing, respectively. MN163 is used for detection in accordance with such a manner that a drain voltage of MN161 is detected to amplify the same, and the resulting voltage is delivered to MP163.
FIG. 18 is a waveform diagram of voltages and electric currents in respective sections of the driving circuit 160 wherein the inverting input terminal 163 is commonly connected with the output terminal 165 to operate the whole arrangement as a voltage follower. In the case shown in FIG. 18, VDD=0 V, VSS=xe2x88x9210 V, the capacitive load C161 is 10,000 pF, and a driving signal Vin (200 xcexcs cycle, and 50% duty) is inputted to the noninverting input terminal 162. In the figure, time is plotted as abscissa and drain voltage Vd(#) of a transistor #, drain current Id(#) of the transistor #, and current consumption Ivdd flowing through the power source VDD as ordinates, respectively. The Ivdd decreased to a value of 67.87 xcexcA at the time of equilibrium. It is to be noted that as to a waveform the polarity of which has been inverted in FIG. 18, xe2x80x9cxe2x88x92xe2x80x9d(bar) is applied over a symbol of the corresponding voltage or electric current.
In the driving circuit 160 when applied for a voltage follower, a step input signal to Vin or a modification of capacitive load C161 causes voltage transition at the output node which is detected and amplified with MN163 to reflect into the drain current of MP163, and the drivability is controlled through the bias current modulation of MP166 and MP167. For instance, when the driving signal input Vin rises, until the output voltage Vout reaches to the same level as of Vin, the drain voltage of MP161 keeps rising that is detected with MP163 to lower its drain voltage and then the drain currents of MP163, MP166 and MP167 are boosted. Namely the output modulation is fed back positively to MP166 and MP167.
Operating currents of MP166 and MP167 in this case are determined by the maximum load current and a current amplification factor in case of positive feedback. In this connection, if the capacitive load C161 is 10,000 pF, 10 mA of electric current is required in the case where the capacitive load C161 is charged to 10V in 10 xcexcs. The current amplification factor in this case is determined by a size ratio of MP164 and MP167. If a current magnification is 100, and when a size ratio of MP164 is set to a value of W/L=40 xcexcm/20 xcexcm=2, it may be set a size ratio of MP167 in such that W/L=600 xcexcm/3 xcexcm=200. An electric current of MP164 in this case is {fraction (1/100)} of 10 mA, so that it becomes 100 xcexcA. When a current amplification factor is made 1000 times larger, a size ratio of MP167 becomes W/L=6000 xcexcm/3 xcexcm=2000, so that it brings about a considerably large transistor. With respect to stability thereof, there is no problem wherein MN163 is operated in class xe2x80x9cBxe2x80x9d or class xe2x80x9cCxe2x80x9d manner so as not to be substantially applied positive feedback in an equilibrium state of the differential amplifying circuit 161.
However, it is theoretically possible to operate the driving circuit 160 stably if an amount of positive feedback is made optimum in a state where positive feedback functions, but open loop gains of MN163 and MP163 become high, so that difficulties are accompanied with a design for maintaining its stability. On the other hand, when open loop gains of MN163 and MP163 are made small, a sufficient positive feedback operation is not carried out. More specifically, there was such a problem that it became critical to set gains of MN163 and MP163. Moreover, when operating points of amplifying operation by means of MN163 and MP163 come near power source voltages, its amplifying circuit itself does not operate normally. Thus, there was also such a problem that it became difficult to solve a pseudo-parasitic oscillating trouble.
A fifth conventional example will be described. FIG. 19 is a circuit diagram showing another conventional driving circuit 180 wherein an output voltage is converted into the form of electric current thereby to drive a load and which has been proposed by IEEE, JSSC, JUNE 1986, xe2x80x9cAn Efficient CMOS Buffer for Driving Large Capacitive Loadsxe2x80x9d. In FIG. 19, reference numerals MP181 to MP187 designate PMOS transistors, MN181 to MN187 NMOS transistors, respectively.
Reference numeral 181 denotes a differential amplifying circuit composed of MP182, MP183, and MN181 through MN183, 182 a noninverting input terminal, 183 an inverting input terminal, 184 an output circuit composed of MN187 and MP187, 185 an output terminal, C181 a capacitive load, and 186 an output driving circuit composed of MP184 to MP186, MN185, and MN186, respectively. A drain of MP183 is directly connected with a gate of MP184, while a drain of MP182 is connected with a gate of MN185 through MP181 and MN184.
In the driving circuit 180 shown in FIG. 19, the inverting input terminal 183 is commonly connected with the output terminal 185, and the whole arrangement thereof functions as a voltage follower. A bias voltage VB181 is applied to a gate of MP186, a bias voltage VB182 is applied to a gate of MN186, and a bias voltage VB183 is applied to a gate of MN183, and there is a relationship of VB181 less than VB182 less than VB183.
The driving circuit 180 is basically a modification of the transconductance amplifier shown in FIG. 15 wherein an electric current corresponding to a drain current of MN182 is reflected to MP184, while an electric current corresponding to a drain current of MN181 is reflected to MN185. This circuit is arranged in such that an output circuit 184 can be fully swung by means of an output driving circuit 186 wherein MP185 functions as a resistance element, whereby a gate voltage of MP187 has a prescribed voltage difference with respect to a gate voltage of MN187, so that simultaneous conduction of both MP187 and MN187 is prevented. Furthermore, MP186 and MN186 are served for affording a gate bias to MP187 and MN187, whereby the latters can effect correct class xe2x80x9cBxe2x80x9d operation.
In also the driving circuit 180, there is such a problem that when a remarkable idling current is not supplied to MP187 and MN187 on the output side, a stable operating point cannot be obtained, although a significant driving force is attained. Besides, there is also such problem that the idling current in the output driving circuit 186 becomes remarkable.
A sixth conventional example will be described. FIG. 20 is a circuit diagram showing a driving circuit 200 wherein two differential amplifying circuits being similar to each other are provided, and one of which is served for a sensor for sensing input signals or changes in output, whereby a driving force of the other differential amplifying circuit or an output circuit is adaptively controlled. Such driving circuit has been proposed by IEEE, JSSC, JUNE 1998, xe2x80x9cA Very-High-Slew-Rate CMOS Operational Amplifierxe2x80x9d and Japanese Unexamined Patent Publication No. 136044/1999. In FIG. 20, reference characters MP201 through MP207 denote PMOS transistors, and MN201 through MN209 NMOS transistors, respectively.
Reference numeral 201 designates a main differential amplifying circuit composed of MP205, MP206, and MN206 to MN208, 202 a noninverting input terminal, 203 an inverting input terminal, 204 an output circuit composed of MP207 and MN209, 205 an output terminal, C201 a capacitive load, 206 a subsidiary differential amplifying circuit composed of MP201 to MP203, MN201, and MN202, and 207 a bias circuit composed of MN203 and MN204 and which is used for the main differential amplifying circuit 201, respectively. A drain of MP206 is directly connected with a gate of MP207, while a drain of MP205 is connected with a gate of MN209 through MP204 and MN205. In other words, the main differential amplifying circuit 201 and the output circuit 204 constitute a transconductance amplifier.
The driving circuit 200 is arranged in such that an electric current of MP201 in the subsidiary differential amplifying circuit 206 is set to be low to keep MN203 and MN204 xe2x80x9cOffxe2x80x9d in equilibrium state, whereby MN203 and MN204 operate in class xe2x80x9cBxe2x80x9d or xe2x80x9cCxe2x80x9d manner. These MN203 and MN204 operate at different operating points one another to detect and amplify a voltage corresponding to a potential difference of differential output of the subsidiary differential amplifying circuit 206, whereby an operating current of the main differential amplifying circuit 201 is increased. In the case when the subsidiary differential amplifying circuit 206 is in the equilibrium state, electric current does not flow through MN203 and MN204, so that the electric current only flows during the positive feedback operation and no useless current flows.
In the driving circuit 200, however, since two differential amplifying circuits are employed, there is a problem of an increase in current consumption. Furthermore, because the main differential amplifying circuit 201 and the output circuit 204 constitute a transconductance amplifier, there is such a problem that a significant idling current must be flowed in the case where a load having a large capacity, as in the above described driving circuits 140 and 180 shown in FIGS. 15 and 19.
A seventh conventional example will be described. FIG. 21 is a circuit diagram showing a driving circuit 220 arranged in such that a current change in a driving waveform is amplified or divided to apply positive feedback thereto, thereby elevating a driving force. Such driving circuit has been proposed by IEEE, JSSC, JUNE, 1990 xe2x80x9cClass AB CMOS Amplifires with High Efficiencyxe2x80x9d. In FIG. 21, reference characters MP221 to MP228 designate PMOS transistors, and MN221 to MN228 NMOS transistors, and I221 to I224 current sources, respectively.
Reference numeral 221 denotes a first differential amplifying circuit composed of MP221, MP222, MN221 through MN223, and the current source I221, 222 a noninverting input terminal, 223 an inverting input terminal, 224 an output circuit composed of MP228 and MN228, 225 an output terminal, C221 a capacitive load, and 226 a second differential amplifying circuit composed of MP226, MP227, MN226, MN227, and I224, respectively.
When an input voltage Vin decreases, a control circuit 227 accompanied with the above described first amplifying circuit 221 and composed of MN223, MN224, MP223, and I222 is allowed to increase an electric current of MN223 to apply positive feedback to the first differential amplifying circuit 221, and at the same time, it is allowed to increase an electric current of MN228 in the output circuit 224. On one hand, when the input voltage Vin increases, a control circuit 228 accompanied with the above described second amplifying circuit 226 and composed of MP224, MP225, MN225, and I223 is allowed to increase an electric current of MP225 to apply positive feedback to the second differential amplifying circuit 226, and at the same time, it is allowed to increase an electric current of MP228 in the output circuit 224.
In the driving circuit 220, positive feedback is applied to an operating current of the first differential amplifying circuit 221 in the case when the input voltage Vin decreases, while positive feedback is applied to an operating current of the second differential amplifying circuit 226 in the case when the input voltage Vin increases. In either of the above cases, the output circuit 224 is remarkably driven, so that its driving force is elevated. An amount of positive feedback applied to the first differential amplifying circuit 221 is determined by a size ratio of MN224 and MN223, while an amount of feedback applied to the second differential amplifying circuit 226 is determined by a size ratio of MP224 and MP225.
In the driving circuit 220, however, since two differential amplifying circuits are used, its consumption current increases. Besides, since MN228 in the output circuit 224 is driven by MN224 and MP228 in the output circuit 224 is driven by MP224, operation of MP228 and that of MN228 in the output circuit 224 become off-balance and unstable, if the feed back operation accomplished with the control circuit 227 and that accomplished with the control circuit 228 do not coincide completely with each other.
Because of this reason, at least several tens xcexcA of idling current is needed in the case where a load having a large capacity is driven in order to achieve a stable operation. When a magnification of positive feedback (a size ratio of MN223 with respect to MN224, and a size ratio of MP225 with respect to MP224) is allowed to increase, it is possible to reduce a magnification of the output transistors MP228 and MN228 (a size ratio of MN228 with respect to MN224, and a size ratio of MP228 with respect to MP224). However, a magnification of positive feedback is self-limited, and there is a limitation in reduction of consumption current. As appeared in page 525 of the above described literary document, when a capacity of the capacitive load C221 is 470 pF or more, performance of 0.25 V/xcexcs slew rate, and 15 times higher current ratio (page 526 of the above described literature) can be attained, but much more improvement is required for driving a liquid crystal panel of 10,000 pF or higher.
As described above, a conventional driving circuit involves a problem of increasing current consumption as a result of useless idling, a problem of a difficulty in handling load variation in a driving circuit wherein an operating current is switched in two steps, and a problem of a difficulty in a design for stable operation in a driving circuit wherein an operating current is varied in response to an input voltage.
An object of the present invention is to provide a driving circuit by which the above described problems can be eliminated.
To solve the above described problem, a driving circuit of the present invention comprises a differential amplifying circuit, an output circuit driven by an output signal of the differential amplifying circuit, and a current control circuit for applying a positive feedback in such that an increased current signal of an operating current on a noninverting side or an operating current on an inverting side of the differential amplifying circuit is injected to increase an operating current of the differential amplifying circuit, wherein a negative feedback for decreasing the increased current signal thus injected is applied to the aforesaid current control circuit.
Furthermore, the aforesaid differential amplifying circuit may comprise a first current mirror circuit for supplying an electric current corresponding to an operating current on the noninverting side to an output section on the inverting side, and a second current mirror circuit for supplying an electric current corresponding to an operating current on the inverting side to an output section on the noninverting side, wherein an increased variation signal of either of the electric current supplied by the first current mirror circuit or the electric current supplied by the second current mirror circuit is injected to the aforesaid current control circuit as the aforesaid increased current signal.
Moreover, the driving circuit of the present invention may comprise a biasing current mirror circuit to add a current being proportional to the aforesaid increased current signal to the operating current of the aforesaid differential amplifying circuit, and a group of negative feedback current mirror circuits which is allowed to decrease the aforesaid increased current signal injected to the current control circuit with the lapse of time are provided.
The aforesaid current control circuit may be provided with a delay capacitor charged by the aforesaid increased current signal thus injected.
Furthermore, the aforesaid biasing current mirror circuit may also be provided with a delay capacitor charged by the aforesaid increased current signal thus injected.
The aforesaid group of the negative feedback current mirror circuits may comprise a first current mirror circuit wherein the aforesaid increased current signal is injected to an output side thereof, a second current mirror circuit wherein an electric current on the output side of the first current mirror circuit flows in an reference side thereof, while an electric current on its output side flows in the reference side of the aforesaid first current mirror circuit and a third current mirror circuit wherein an electric current on the reference side of the aforesaid first current mirror circuit flows in its reference side, while an electric current on its output side flows in the output side of the aforesaid first current mirror circuit, and each magnification of the aforesaid first, second, and third current mirror circuits is set to a predetermined value, whereby the aforesaid increased current signal thus injected is allowed to decrease.
The aforesaid output circuit may be constituted in such that a first transistor driven in response to an increased current signal of either of the operating current on the noninverting side or the operating current on the inverting side of the aforesaid differential amplifying circuit and a second transistor driven by a fixed bias voltage are connected serially between a high potential power source and a low potential power source, common connecting points of both the transistors are served for an output terminal, and a third transistor is connected in parallel to the aforesaid second transistor; and the current control circuit to which is injected the other increased current signal of the operating current on the noninverting side or the operating current on the inverting side of the aforesaid differential amplifying circuit is provided with a load resistance for converting the aforesaid increased current signal thus injected into a voltage; whereby the aforesaid third transistor is driven by the voltage produced in the load resistance.